At Intel, we work every single day to design and manufacture silicon products as the fundamental building blocks that empower people's digital lives. Do you love contributing to flagship products in cutting edge process nodes? Do you love solving technical challenges that no one has solved yet? Do you enjoy working with cross-functional teams to deliver solutions for products that impact customers' lives?
Intel's Design Methodology Enablement (DME) team is looking for an experienced senior physical design engineer to help define tools, flows, and methodologies (TFM) for development of Intel's flagship Networking and Edge products.
You will be responsible for, but not limited to:
- Participate and lead others in developing TFM automation and enhancements.
- Contributions towards the physical design system and physical implementation (floorplanning, power grid insertion, placement, CTS, route).
- Opportunity to work closely with RTL teams, SD teams, and EDA tool vendors.
Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Establishes regression flows, drives improvement in RTL to GDS flows, and creates and implements methodologies for improving robustness, power, performance, area, and timing for optimizing physical design constraints. Develops new physical design techniques through innovative scripts, checkers, flows, and other CADbased automation to simplify and expedite the design process. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing physical design related TFM. Partners with physical design, circuits, CAD, RTL, tool/flow owners, and thirdparty vendor teams to continuously improve physical design methodologies and efficiencies.
**Qualifications**:
- Master's degree in electrical or computer engineering with 10+ years of industry experience or bachelor's degree with 13+ years of industry experience.
- Expert in physical design methodologies and sub-micron technology Place and Route (Fusion Compiler).
- Tcl/Perl/Python coding skills to automate design process and improve efficiency in EDA tool suites.
- Highly experienced in static timing analysis (PrimeTime).
- Strong verbal and written communication skills in English.
- Excellent teamwork skills including ability to work with multiple and remote groups worldwide.
- Motivated self-starter, with strong ability to work independently as well as in a team environment.
- Flexibility and maturity in facing uncertainties and changing priorities/responsibilities.
- Act with velocity and a strong sense of urgency.
- Respect cultural diversity and sensitivity.
- Agility in learning, improving, and innovating.
- Experience with physical verification (DRC/LVS/Antenna), EM/IR-Drop/Xtalk analysis (PT-SI), and formal verification (Formality or LEC).
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.