**Position Overview**
This exciting new Verification Engineer position within the Design Verification Technologies Group at Siemens EDA reports to the Technical Product Manager for the Design Verification Technology division. In the role of Verification Engineer, you will join a strong team that is rapidly growing its business in a fast-growing market segment!
**Responsibilities**
- Develop and maintain SystemVerilog models or components within those models
- Write testcases/compliance testcases to verify functionality of customer DUTs and the VIP itself
- Analyze simulation reports and debug failures in both internal regressions and customer reported issues
- Stay up to date with the latest SystemVerilog features, simulator simulation and debug features
- Stay up to date with protocol specific features (Protocol Specification updates) and develop feature enhancement plans along with other team members
- This role may require travel to the US or other locations from time to time, so strong communication skills and ability to proactively work to resolve customer questions and issues is important.
**Required Knowledge/Skills, Education, and Experience**
- Bachelor's degree or master's degree in Electrical or Computer Engineering
- Must possess excellent problem solving and debug skills.
- Experience in developing SystemVerilog / UVM based testbenches
- Experience in working with industry standard protocols like AXI, USB, PCIe or others.
- Strong background on functional verification fundamentals, like environment planning, test plan generation, environment development.
- Experience in using industry standard simulation and debug tools like QuestaPrime, VCS, Xcellium simulators, Verdi, DVE, etc..
**About Siemens EDA Verification IP Solutions**
Siemens EDA recently completed a successful acquisition of Avery Design Systems to create the industry's most comprehensive Verification IP solutions. Siemens EDA automates verification and debug of complex SoCs and FPGAs, dramatically increasing productivity and helping companies manage resources more efficiently. Siemens EDA's best-in-class technologies maximize the effectiveness of verification at the block, subsystem, and system levels.
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