Responsible for ensuring the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp.
Make significant contributions to design, development and validation of testability circuits.
Evaluation, development and debug of complex test methods.
Develops and debugs complex software programs to convert design validation vectors and drive complex test equipment.
Creates and tests validation and production test hardware solutions.
Tests, validates, modifies and redesigns circuits to guarantee component margin to specification.
Analyzes and evaluates component specification versus performance to ensure optimal match of component requirements with production equipment capability with specific emphasis on yield analysis and bin split capability.
Analyzes early customer returns with emphasis on driving test hole closure activities.
Creates and applies concepts for optimizing component production relative to both quality and cost constraints.
Autonomously plans and schedules own daily tasks, develops solutions to problems utilizing formal education and judgment.
Behavioral traits desired for this position:
- Ability to effectively work with cross functional teams across geographies.
- Oral and written communication skills including written test plans and presenting to live and virtual audiences.
- Critical thinking and problem solving skills to debug circuits and make recommendations to design teams.
**Qualifications**
**Minimum Qualifications**:
- BSc Degree in Electrical Engineering or related field OR related experience in lieu of degree
- Experience with test or test equipment to support debug and characterization of SOC/ASICs.
- Intermediate to Advanced English level
**Preferable qualifications**:
- Knowledge of Verilog/System Verilog, RTL design and micro-architecture skills
- trong knowledge of SoC tools/methodology ( VCS, Synthesis, Tessent Industry standard ATPG/MBIST tools design compiler etc.).
- Experiences in a programing language such as C/C++ Perl/Python/TCL scripting
- Simulation and validation experience with hardware description languages such as Verilog and/or System Verilog.
- Knowledge of Test Program development on High Volume Manufacturing (HVM) testers/ Platforms.
- Knowledge of DFT architectures and methodologies in any of the following areas: Scan, ATPG, Mbist, BScan, IO DFx, analog DFT, JTAG, Boundary scan etcKnowledge of DFT architectures and methodologies in any of the following areas: Scan, ATPG, Mbist, BScan, IO DFx, analog DFT, JTAG, Boundary scan etc
- Knowledge of Intel CPU/SOC or other ASIC architecture, scripting/programing and UNIX.
**Inside this Business Group**
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products.
From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations.
DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams.
As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
**Work Model for this Role**
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.